FIG. 1 is a cross-sectional view of a wiring substrate 100 according to a related art example. With reference to FIG. 1, the wiring substrate 100 includes a first wiring layer 110, a first insulation layer 120, a second wiring layer 130, a second insulation layer 140, a third wiring layer 150, a third insulation layer 160, a fourth wiring layer 170, and a fourth insulation layer 180.
Each of the first wiring layer 110, the second wiring layer 130, the third wiring layer 150, and the fourth wiring layer 170 is formed of, for example, copper (Cu). Each of the first insulation layer 120, the second insulation layer 140, the third insulation layer 160, and the fourth insulation layer 180 is formed of, for example, an epoxy type insulation resin.
The first wiring layer 110 and the second wiring layer 130 are electrically connected via first via holes 120x. The second wiring layer 130 and the third wiring layer 150 are electrically connected via second via holes 140x. The third wiring layer 150 and the fourth wiring layer 170 are electrically connected via third via holes 160x. 
A side surface of the first wiring layer 110 and an upper surface of the first wiring layer 110 (a first surface of the first wiring layer 110 that is connected to a via wiring of the second wiring layer) are covered by the first insulation layer 120. Parts of a bottom surface of the first wiring layer 110 (a second surface of the first wiring layer 110 located opposite to the first surface) are exposed at the first insulation layer 120. The exposed parts of the bottom surface of the first wiring layer 110 act as electrode pads for electrically connecting the wiring substrate 100 to a semiconductor chip or the like (not illustrated). Parts of the fourth wiring layer 170 are exposed at opening parts 180x formed in the fourth insulation layer 180. The exposed parts of the fourth wiring layer 170 act as electrode pads for electrically connecting the wiring substrate 100 to a mounting substrate such as a motherboard (not illustrated). The pitch between the exposed parts of the bottom surface of the wiring layer 110 is narrower than the pitch between the exposed parts of the fourth insulation layer 170.
The first, second, and third insulation layers 120, 140, 160 are formed of, for example, an insulation resin having a non-photosensitive property. The first, second, and third insulation layers 120, 140, 160 contain, for example, fillers including less than 30 vol % silica (SiO2). The thermal expansion coefficient of the first, second, and third insulation layers 120, 140, 160 is, for example, approximately 50 ppm/° C.
The fourth insulation layer 180 is formed of, for example, an insulation resin having a photosensitive property. The fourth insulation layer 180 also contains fillers. However, because exposing cannot be performed in a case where a large amount of filler is contained in an insulation resin having a photosensitive property, there is a limit (upper limit) in the amount of filler that can be contained in the fourth insulation resin 180. Therefore, the thermal expansion coefficient of the fourth insulation layer 180 is greater than the thermal expansion coefficient of the first insulation layer 120, the second insulation layer 140, and the third insulation layer 160. For example the thermal expansion coefficient of the fourth insulation layer 180 is, for example, approximately 65 ppm/° C.
Thus, only the uppermost insulation layer (e.g., fourth insulation layer 180 of FIG. 1) of a related art wiring substrate is formed of an insulation resin having a photosensitive property. Typically, insulation layers of the related art wiring substrate other than the uppermost insulation layer (e.g., first insulation layer 120, second insulation layer 140, third insulation layer 160 of FIG. 1) are formed of an insulation resin having a non-photosensitive property and containing a filler including less than 30 vol. % silica (SiO2).
As illustrated in FIG. 1, the side of the wiring substrate 100 toward the first wiring layer 110 (i.e. the side of the wiring substrate 100 including electrode pads to be connected to a semiconductor chip or the like (not illustrated)) tends to warp (curve) into a concave shape in a case where the configuration of the wiring substrate 100 includes an uppermost insulation layer (i.e. fourth insulation layer 180) formed of an insulation resin having a photosensitive property and other insulation layers besides the uppermost layer (i.e. first insulation layer 120, second insulation layer 140, third insulation layer 160) formed of an insulation resin having a non-photosensitive property and containing a filler including less than 30 vol. % silica (SiO2). That is, the wiring substrate 100 tends to warp toward the side of the wiring substrate 100 at which the electrode pads are formed (“semiconductor chip mounting side” of the wiring substrate 100). Further, the wiring substrate 100 having such configuration may have a warp T1 exceeding 600 μm.
The tendency of warping and the amount of warping are substantially the same as those of the configuration of the wiring substrate 100 illustrated in FIG. 1 even in a case of a configuration in which an uppermost insulation layer (i.e. fourth insulation layer 180) is formed of an insulation resin having a non-photosensitive property and all of the insulation layers (i.e. first insulation layer 120, second insulation layer 140, third insulation layer 160, fourth insulation layer 180) are formed of an insulation resin having a non-photosensitive property and containing a filler including less than 30 vol. % silica (SiO2).